Khalil Monfaredi

PhD Thesis Defense Session

Abstract:
Considering the subject of this thesis which is about low voltage low power current steering digital to analog converters design for high definition video applications, in first step with a wide and comparative approach different types of DACs and more specially the well improved ones are investigated. This procedure resulted in selection of appropriate DAC type for intended high precision and high speed application. Then, considering the fact that every DAC includes two digital and analog parts, and since the analog part has more tremendous effect than digital part on DAC’s overall performance, we focused mainly on improving current mirror, current buffer, and deglitching parts and successfully designed some novel structures which resulted in several international papers.
Some achievements of this thesis are the design of high performance current mirrors as one of the main building blocks of current steering DACs. Ultra high output resistance (400GΩ), low voltage supply (0.9V), Ultra low current transfer error (3*10-3%), very low input resistance (0.0058Ω), ultra high input and output compliance (0.058V and 0.055V, respectively), very low offset and power dissipation (0.4aA and 86nW, respectively), wide dynamic range and bandwidth (150dB and 210MHz, respectively) are some of improvements we achieved during current mirror design phase in this thesis.
One of the current mirrors which was the perfect choice for providing ultra wide dynamic range, low power consumption, very high output resistance, good precision and minimum voltages at input and output nodes was selected for designing the current steering DAC promised in this thesis. The other important and determinative analog part of current steering DAC is its output section which has a tremendous effect on producing glitch, speed and the effective number of bits. This forced us to put a strong emphasis on proposing improved structures for this (output) part. Utilizing the mentioned current mirror with ultra wide dynamic range, low power consumption, very high output resistance, good precision and minimum voltages at input and output nodes, and also the novel current buffer cell with outstanding deglitching scheme whose wonderful capability is mainly due to its ultra fast settling time, local deglitching, and statistical glitch division schemes, realized most of the aforementioned goals and resulted in design of ultra high speed current steering DAC (2GS/s) with 12Bit precision and high SFDR (73.43dB), very low glitch (0.42PV*s), low supply voltage (1V) and low power consumption (3.446mW). This DAC is perfectly suitable for mixed mode, HDTV, and high speed applications in which large glitch energy is considered as the main issues. Whereas most of the previously reported artworks suffer from high power consumption and high glitch energy. The operation of proposed structures is proved by HSPICE simulations in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology.

Defense Date: 19 October 2011 Time: 14
Location: Seminar Hall, Electronic Research Center, Iran University of Science and Technology, Narmak, Tehran, Iran