Volume 5, Issue 4 (December 2009)                   IJEEE 2009, 5(4): 223-229 | Back to browse issues page

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Miar- Naimi H, Zabihi M. Nonlinear optimized Fast Locking PLLs Using Genetic Algorithm. IJEEE 2009; 5 (4) :223-229
URL: http://ijeee.iust.ac.ir/article-1-188-en.html
Nonlinear optimized Fast Locking PLLs Using Genetic Algorithm
H. Miar- Naimi , M. Zabihi
Abstract:   (7939 Views)
Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the performance of the proposed structure, various tests performed and results compared with standard phase locked loop. The tests and results show the superior performance of the proposed PLL.
Keywords: PLL , Genetic Algorithm , Nonlinear Element , Fast Lock
Full-Text [PDF 580 kb]   (3296 Downloads)    
Type of Study: Research Paper | Subject: Analog Circuits
Received: 2009/09/14 | Revised: 2011/12/25 | Accepted: 2011/06/19
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.