Volume 19, Issue 2 (June 2023)                   IJEEE 2023, 19(2): 2277-2277 | Back to browse issues page

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Hamidi A, Karimi S, Ahmadi A. Impact of Sampling Frequency on Implementation Cost and Performance of FPGA-based Digital Controller of Power Converters: Case Study for Three-Phase Four-Legs Inverters. IJEEE 2023; 19 (2) :2277-2277
URL: http://ijeee.iust.ac.ir/article-1-2277-en.html
Impact of Sampling Frequency on Implementation Cost and Performance of FPGA-based Digital Controller of Power Converters: Case Study for Three-Phase Four-Legs Inverters
A. Hamidi , S. Karimi , A. Ahmadi
Abstract:   (1571 Views)
One of the problems in digital control of power converters is calculation time in each sampling instant which effect on cost and complexity of digital controller. In this paper, a formula is introduced for calculating the number of clock cycles in each sample then interaction between sampling frequency and implementation cost (number of functional units and word length) of FPGA-based digital controller of DC-AC converter (three-phase four-legs inverter) is verified. The digital architecture is built on finite set model predictive control, and implemented on the FPGA board based on fixed-point calculations. We consider two digital architectures for design the controller in this study. One with four functional units and another with six functional units. This study aims to develop a mathematical equation for the number of clock cycles in each time instant to select the best switching state in the control algorithm, which affects the sampling frequency and clock frequency. Based on the obtained results, the number of functional units, word-length, and the number of switches determine the maximum clock cycles. By knowing maximum clock cycles the maximum sampling frequency is determined. In structure with four functional units, the maximum sampling frequency is 71 kHz for WL=8 bits and 17.7 kHz for WL=32 bits, and in structure, with six functional units, the maximum sampling frequencies are 97.6 and 24.4 kHz for WL=8 and WL=32 bits, respectively. In architecture with more functional units, we have greater sampling frequency with more accuracy and cost. The results obtained from this paper can be a reference for digital controller design. 
Keywords: Sampling Frequency, Digital Architecture, Functional Units, Word Length, Implementation Cost, Three-phase Inverter.
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Type of Study: Research Paper | Subject: VLSI
Received: 2021/09/07 | Revised: 2023/06/06 | Accepted: 2023/06/11
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.