M. Piry, M. Khanjani Moaf, P. Amiri,
Volume 10, Issue 1 (3-2014)
Abstract
Class-AB circuits, which are able to deal with currents several orders of magnitude larger than their quiescent current, are good candidates for low-power and high slew-rate analog design. This paper presents a novel topology of a class AB flipped voltage follower (FVF) that has better slew rate and the same power consumption as the conventional class-AB FVF buffer previously presented in literature. It is thus suitable for low-voltage and low-power stages requiring low bias currents. These buffers have been simulated using 0.5µm CMOS Technology models provided by IBM. The buffer consumes 20µA from a 0.9V supply and has a bandwidth of 50MHz with a 18pF load. It has a slew rate of 9.8V/µs and power consumption of 42µw
T. Azadmousavi, H. Faraji Baghtash, E. Najafi Aghdam,
Volume 14, Issue 2 (6-2018)
Abstract
This work introduces a new and simple method for adjusting the gain of current mirror. The major advantage of the proposed architecture is that, unlike the conventional variable gain current mirror, it does not need the change of the biasing current to adjust current gain. Therefore, the power dissipation remains constant in all of the gain settings. In addition, the proposed variable gain current mirror have linear-in-dB gain control characteristic, simple structure, and small occupied area. The gain of the current mirror can be simply varied from 1.3dB to 21dB while the 3-dB bandwidth of the circuit remains around 12.3MHz or 33.6MHz at operation frequency range of 1.9MHz-14.2MHz and 6.6MHz-40.2MHz respectively. The proposed circuit draws negligible power of 6.9µW from 1.8V supply voltage. The simulation results of designed variable gain current mirror in 0.18μm standard CMOS technology confirms the effectiveness of the proposed circuit.
M. Soleimani, S. Toofan,
Volume 14, Issue 3 (9-2018)
Abstract
This paper presents a high-speed, low-power and low area encoder for implementation of flash ADCs. Key technique for design of this encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-input compound AND-OR gates. In the second stage by two ROM encoders, 2-of-M codes determine n-1 MSB bits and one LSB bit. The advantages of the proposed encoder rather than other similar works are high speed, low power consumption, low active area, and low latency with same bubble error removing capability. To demonstrate the mention specifications, 5-bit flash ADCs with conventional and proposed encoders in their encoder blocks, are simulated at 2-GS/s and 3.5-GS/s sampling rates in 0.18-μm CMOS process. Simulation results show that the ENOB of flash ADCs with conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined almost 30-ps faster rather than the conventional encoder at 2-GS/s. Also, the power consumptions of the conventional and proposed encoders were 17.94-mW and 11.74-mW at 3.5-GS/s sampling rate from a 1.8-V supply, respectively. Corresponding, latencies of the conventional and proposed encoders were 3 and 2 clock cycles. In this case, number of TSPC D-FFs and logic gates of the proposed encoder is decreased almost 39% compared to the conventional encoder.
M. Tahmasebipour, M. Modarres,
Volume 14, Issue 4 (12-2018)
Abstract
In this paper, a highly sensitive piezoresistive differential pressure microsensor is proposed. This microsensor is consisted of a silicon microcantilever (Length=145 µm; Width=100 µm; Thickness=0.29 µm) and two piezoresistors were mounted (via proper connections) on the microsensor for measuring the created pressure difference. Applying pressure to the microcantilever induces longitudinal and transverse stresses in the piezoresistors, changing their electric resistance and, consequently, the output voltage in the reading circuit of the microsensor. Longitudinal and transverse stresses, different relative sensor resistances resulting from different pressures, voltage variations along the piezoresistors, and microcantilever deflection resulting from different pressures were investigated. To improve the sensor sensitivity, effect of doping concentration, piezoresistors width, and the width of the structure placed under the piezoresistors were studied. In addition, we studied how increasing the width and length of the beam influenced the sensitivity of the sensor. Based on analysis results, the sensor sensitivity was increased from 0.26 W/Pa to 15.78 W/Pa (~60 times). To evaluate the behavior and performance of the proposed microsensor, the following characteristics were analyzed: maximum microcantilever displacement, von Mises stress distribution along the beam and microsensor resistance variations.
M. El Alaoui, F. Farah, K. El Khadiri, H. Qjidaa, A. Aarab, A. Lakhssassi, A. Tahiri,
Volume 15, Issue 4 (12-2019)
Abstract
In this work, the design and analysis of new Level Shifter with Gate Driver for Li-Ion battery charger is proposed for high speed and low area in 180nm CMOS technology. The new proposed level shifter is used to raise the voltage level and significantly reduces transfer delay 1.3ns (transfer delay of conventional level shifter) to 0.15ns with the same input signal. Also, the level shifter with gate driver achieves a propagation delay of less than 0.25ns and the total area is only 0.05mm2. The proposed level shifter with gate driver was designed, simulated and layouted in Cadence using TSMC 180nm CMOS technology.
