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Showing 3 results for Azhari
A Novel Very High Performance CMOS Current Mirror with extremely low input and ultra high output resistance
H. Faraji Baghtash, S. J. Azhari, Kh. Monfaredi,
Volume 7, Issue 4 (December 2011)
Abstract
In this paper a novel very high performance current mirror is presented. It favorably benefits from such excellent parameters as: Ultra high output resistance (36.9GΩ), extremely low input resistance (0.0058Ω), low output (~0.18V) and low input voltage (~0.18V) operation, very low power consumption (20μW), very low offset current (1pA), ultra wide current dynamic range (150dB), and ultra high accuracy (error = 0.003%). The circuit has a very simple compact architecture and uses a single 1V power supply. The qualitative performance of the circuit is validated with HSPICE simulations using HSPICE TSMC 0.18μm CMOS technology.
An Ultra High CMRR Low Voltage Low Power Fully Differential Current Operational Amplifier (COA)
A. Roohavar, S. J. Azhari,
Volume 11, Issue 4 (December 2015)
Abstract

this paper presents a novel fully differential (FD) ultra high common mode rejection ratio (CMRR) current operational amplifier (COA) with very low input impedance. Its FD structure that attenuates common mode signals over all stages grants ultra high CMRR and power supply rejection ratio (PSRR) that makes it suitable for mixed mode and accurate applications. Its performance is verified by HSPICE simulations using TSMC 0.18µm CMOS technology and ±0.75V supply voltage that indicate such outstanding results of 81.1dB gain,298MHz gain-bandwidth product, 64º phase margin, 28.2m&Omega input impedance, 159dB CMRR and PSRR+/PSRR- of 174dB/163dB all at low power consumption of 0.302mW.To study the robustness of the COA against technology and get such results close to measurement, Monte Carlo analysis is applied on both pre- layout and post layout simulations of the design. The results are as 73.29dB and 2.07MHz, 1.92&Omega, and150.35dB for Ai magnitude and bandwidth, Ri, and CMRR, respectively, in pre-layout case while change to 66.58dB and 1.44 MHz, 11.07 &Omega, and 147.10dB, for the same arrange, in post layout case. These measurement-like results thus, prove excellent practical performance of the proposed COA.

AWT IMAGE


A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer
S. J. Azhari, M. Zareie,
Volume 15, Issue 2 (June 2019)
Abstract
In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single input-single output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under ±0.75 V by Cadence using TSMC 0.18 µm CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very low values of input impedance under low supply voltages and low power dissipation. The most important parameters of 1st, 2nd and 3rd orders, i.e. input impedance (Rin), -3 dB bandwidth (BW), power dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as:
1st order: Rin (52.4 Ω), BW (733.7 MHz), Pd (225.6 µW), Ro (105.6 kΩ)
2nd order: Rin (3.8 Ω), BW (576.4 MHz), Pd (307 µW), Ro (106.4 kΩ)
3rd order: Rin (0.34 Ω), BW (566.9 MHz), Pd (535.6 µW), Ro (118.2 kΩ)
And in Post-layout plus Monte Carlo results as:
1st order: Rin (59.9 Ω), BW (609.6 MHz), Pd (212.4 µW), Ro (106.9 kΩ)
2nd order: Rin (11.3 Ω), BW (529.3 MHz), Pd (389.9 µW), Ro (109.8 kΩ)
3rd order: Rin (5.8 Ω), BW (526.5 MHz), Pd (514.5 µW), Ro (125.5 kΩ)
Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block.

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.