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Differential Power Analysis (DPA) implies measuring the supply current of a cipher-circuit in an attempt to uncover part of a cipher key. Cryptographic security gets compromised if the current waveforms obtained correlate with those from a hypothetical power model of the circuit. As FPGAs are becoming integral parts of embedded systems and increasingly popular for cryptographic applications and rapid prototyping, it is imperative to consider security on FPGAs as a whole. During last years, there has been a large amount of work done dealing with the algorithmic and architectural aspects of cryptographic schemes implemented on FPGAs, however, there are only a few articles that assess their vulnerability to such attacks which, in practice, pose far a greater danger than algorithmic attacks. This paper first demonstrates the vulnerability of the Advanced Encryption Standard Algorithm (AES) implemented on a FPGA and then presents a novel approach for implementation of the AES algorithm which provides a significantly improved strength against differential power analysis with a minimal additional hardware overhead. The efficiency of the proposed technique was verified by practical results obtained from real implementation on a Xilinx Spartan-II FPGA.

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A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. The results we obtained show that with G = 55 our proposed design is able to compute GF(2163) elliptic curve scalar multiplication in 9.6 μs with the maximum achievable frequency of 250 MHz on Xilinx Virtex-4 (XC4VLX200), where G is the digit size of the underlying digit-serial finite field multiplier. Another implementation variant for less resource consumption is also proposed. With G=33, the design performs the same operation in 11.6 μs at 263 MHz on the same platform. The results of synthesis show that in the first implementation 17929 slices or 20% of the chip area is occupied which makes it suitable for speed critical cryptographic applications while in the second implementation 14203 slices or 16% of the chip area is utilized which makes it suitable for applications that may require speed-area trade-off. The new design shows superior performance compared to the previously reported designs.

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In this work, a broadband dual-channel differential phase shifter is developed with a small phase deviation across a wide frequency range. The design consists of two main lines for 45° and 90° phase shifts, along with a reference line. A prototype is fabricated and measured to validate the performance of the design. Phase shifts of 45° ± 5° and 90° ± 5° over a frequency range of 1.26 GHz - 4 GHz (bandwidth of 104%) are achieved from the channels. The transmission losses of the three lines are less than 0.35 dB and the isolation between the adjacent ports is better than 20 dB. The area of this dual-channel differential phase shifter is  (14.7 mm × 66.15 mm), where is the guided wavelength at the center frequency.