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P. Bhat Nempu, J. N. Sabhahit,
Volume 16, Issue 4 (December 2020)
Abstract

The hybrid AC-DC microgrid (HMG) architecture has the merits of both DC and AC coupled structures. Microgrids are subject to intermittence when the renewable sources are used. In the HMG, since power fluctuations occur on both subgrids due to varying load and unpredictable power generation from renewable sources, proper voltage and frequency regulation is the critical issue. This article proposes a unique method for operating a microgrid (MG) comprising of PV array, wind energy system (WES), fuel cell (FC), and battery in HMG configuration. The control scheme of the interlinking converter (ILC) regulates frequency, voltage, and power flow amongst the subgrids. Power management in the HMG is investigated under different scenarios. Proper power management is accomplished within the individual subgrids and among the subgrids by the control techniques adopted in the HMG. The system voltage and frequency deviations are found to be minimized when the FC system acts as the backup source for DC subgrid, reducing the power flow through the ILC.

R. Samanth, S. G. Nayak, P. B. Nempu,
Volume 19, Issue 1 (March 2023)
Abstract

In the CMOS circuit power dissipation is a major concern for VLSI functional units. With shrinking feature size, increased frequency and power dissipation on the data bus have become the most important factor compared to other parts of the functional units. One of the most important functional units in any processor is the Multiply-Accumulator unit (MAC). The current work focuses on the development of MAC unit bus encoders as well as the identification of an improved architecture for image processing applications. To reduce the power consumption in these functional units, two bus encoding architectures were developed by encoding data before it was sent on the data buses. One is MSB reference encoding, and another is Fourth and Fifth bit ANDing (FFA) without the need for an extra bus line with fewer transitions by using gray codes. The comparison of the proposed encoding architectures with the existing encoding architectures from the literature revealed an 8% to 36% significant improvement in power dissipation. The simulation was done with Xilinx ISE, and the Cadence RTL Compiler tool was utilized for the synthesis, which was done with the 180nm technology library. And also, the image filtering is analyzed using MATLAB.


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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.