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Showing 3 results for Carbon Nanotube
Application of Neural Space Mapping for Modeling Ballistic Carbon Nanotube Transistors
R. Yousefi, M. K. Moravvej-Farshi, K. Saghafi,
Volume 6, Issue 2 (6-2010)
Abstract
In this paper, using the neural space mapping (NSM) concept, we present a SPICE-compatible modeling technique to modify the conventional MOSFET equations, to be suitable for ballistic carbon nanotube transistors (CNTTs). We used the NSM concept in order to correct conventional MOSFET equations so that they could be used for carbon nanotube transistors. To demonstrate the accuracy of our model, we have compared our results with those obtained by using open-source software known as FETToy. This comparison shows that the RMS errors in our calculated IDS, under various conditions, are smaller than the RMS errors in IDS values calculated by the existing analytical models published by others.
Ultra-Low Power 5T-SRAM Cell Design using different CNTFET for exploiting Read/Write Assist Techniques
G. S. Kumar, G. Mamatha,
Volume 19, Issue 1 (3-2023)
Abstract
In today's technological environment, designing the Static Random Access Memory (SRAM) is most vital and critical memory devices. In this manuscript, two kinds of 5TSRAM are designed using different CNTFET such as Dual-ChiralityGate all around (GAA) CNTFET and Ballistic wrap gate CNTFET based 5T SRAM cell designs for enhancing the read/write assist process. Here, the proposed Dual-ChiralityGAA-CNTFET based 5T-SRAM has two cross-coupled inverters using one access transistor that is connected to the bit line (BL) and word line (WL) through minimum supply voltage. Instead of cross-coupled inverter circuit, the BWG-CNTFET based 5T-SRAM cell is intended for achieving less power and improved read/write assist process. Also, one transistor is executed as low-threshold (LVT) device in the proposed BWG-CNTFET based 5T-SRAM. Thus, proposed two kinds of 5T SRAM cells increases the read/write assist operation and reduce the leakage current/ power. The simulation of the proposed two kinds of 5T SRAM cell is done by HSPICE simulation tool and the performance metrics are calculated. Therefore, the proposed Dual-ChiralityGAA-CNTFET based 5T-SRAM cell design has attained 11.31%, 51.47% lower read delay, 44.44%, 26.33% lower write delay, 36.12%, 45.28% lower read power, 34.5% , 22.41% lower write power, 37.4%, 15.3% higher read SNM and 35.8%, 12.09% higher write SNM than Double gate carbon nanotube field effect transistors (DG CNTFET) and state-of-art method respectively. Similarly, the proposed BWG-CNTFET 5T SRAM cell design has attained 45.53%, 38.77% lower write delay, 56.67%, 45.64% lower read delay, 58.4%, 56.75% lower read power, 49.66%, 28.56% lower write power, 35.32%, 12.7% higher read SNM and 45.8%, 15.6% higher write SNM than Reduced Power with Enhanced Speed (RPES) approach and state-of-art method respectively.

Carbon Nanotube Based Variation Tolerant Low Power Cache Memory for 5G Networks
Kavitha Manickam, P.k. Janani, S. Karthick, S. Arulsivam, C. Vikram, G. Hariharan, R. Kavinkumar, P. Ganesh,
Volume 20, Issue 2 (6-2024)
Abstract
The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power. The prime interest of this article is to design a memory structure which is tolerant to variations in CNFET (Carbon nanotube field effect transistor) parameters like pitch, diameter and number of CNT tubes, and also offer low power and high speed of operation. In this context, CNFET based stacked SRAM (Static random access memory) design is proposed to attain the above mentioned criteria. Concept of stack effect is utilized in the cross coupled inverter section of the memory structure to attain low power. The power, speed and energy analysis for the proposed structure is done, and compared with the conventional structures to justify the proposed memory cell performance. HSPICE simulation results has confirmed that the proposed structure offers about 34%, 54% and 95% power saving in hold mode, read mode and write mode respectively. In speed and energy point of view it provides about 97% read delay, 92% write delay and 98% energy savings than the conventional memory structures. These results make it clear that the proposed SRAM is suitable for the 5G networks where circuit speed, power and energy consumption are the major concern.

 
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.