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Showing 2 results for Current Buffer
A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer
S. J. Azhari, M. Zareie,
Volume 15, Issue 2 (6-2019)
Abstract
In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single input-single output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under ±0.75 V by Cadence using TSMC 0.18 µm CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very low values of input impedance under low supply voltages and low power dissipation. The most important parameters of 1st, 2nd and 3rd orders, i.e. input impedance (Rin), -3 dB bandwidth (BW), power dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as:
1st order: Rin (52.4 Ω), BW (733.7 MHz), Pd (225.6 µW), Ro (105.6 kΩ)
2nd order: Rin (3.8 Ω), BW (576.4 MHz), Pd (307 µW), Ro (106.4 kΩ)
3rd order: Rin (0.34 Ω), BW (566.9 MHz), Pd (535.6 µW), Ro (118.2 kΩ)
And in Post-layout plus Monte Carlo results as:
1st order: Rin (59.9 Ω), BW (609.6 MHz), Pd (212.4 µW), Ro (106.9 kΩ)
2nd order: Rin (11.3 Ω), BW (529.3 MHz), Pd (389.9 µW), Ro (109.8 kΩ)
3rd order: Rin (5.8 Ω), BW (526.5 MHz), Pd (514.5 µW), Ro (125.5 kΩ)
Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block.

Design of Gate-Driven Quasi Floating Bulk OTA-Based Gm–C Filter for PLL Applications
P. Gupta, S. K. Jana,
Volume 17, Issue 2 (6-2021)
Abstract
The advancement in the integrated circuit design has developed the demand for low voltage portable analog devices in the market. This demand has increased the requirement of the low-power RF transceiver. A low-power phase lock loop (PLL) is always desirable to fulfill the need for a low power RF transceiver. This paper deals with the designing of the low power transconductance- capacitance (Gm-C) based loop filter with the help of the gate-driven quasi bloating Bulk (GD-QFB) MOS technique. The GD-QFB MOS-based operational transconductance amplifier (OTA) has been proposed with a high dc gain of 82.41 dB and less power consumption of 188.72 µW. Further, Gm-C based active filter has been designed with the help of the proposed GD-QFB OTA. The simulation results of Gm-C filter attain a -3 dB cut-off frequency of 59.08 MHz and power consumption of 188.31µW at the supply voltage of 1V. The proposed Gm-C filter is suitable for the designing of 1-3 GHz low power PLL.

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.