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Showing 4 results for Current Mode
An Ultra High CMRR Low Voltage Low Power Fully Differential Current Operational Amplifier (COA)
A. Roohavar, S. J. Azhari,
Volume 11, Issue 4 (12-2015)
Abstract

this paper presents a novel fully differential (FD) ultra high common mode rejection ratio (CMRR) current operational amplifier (COA) with very low input impedance. Its FD structure that attenuates common mode signals over all stages grants ultra high CMRR and power supply rejection ratio (PSRR) that makes it suitable for mixed mode and accurate applications. Its performance is verified by HSPICE simulations using TSMC 0.18µm CMOS technology and ±0.75V supply voltage that indicate such outstanding results of 81.1dB gain,298MHz gain-bandwidth product, 64º phase margin, 28.2m&Omega input impedance, 159dB CMRR and PSRR+/PSRR- of 174dB/163dB all at low power consumption of 0.302mW.To study the robustness of the COA against technology and get such results close to measurement, Monte Carlo analysis is applied on both pre- layout and post layout simulations of the design. The results are as 73.29dB and 2.07MHz, 1.92&Omega, and150.35dB for Ai magnitude and bandwidth, Ri, and CMRR, respectively, in pre-layout case while change to 66.58dB and 1.44 MHz, 11.07 &Omega, and 147.10dB, for the same arrange, in post layout case. These measurement-like results thus, prove excellent practical performance of the proposed COA.

AWT IMAGE


A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer
S. J. Azhari, M. Zareie,
Volume 15, Issue 2 (6-2019)
Abstract
In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single input-single output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under ±0.75 V by Cadence using TSMC 0.18 µm CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very low values of input impedance under low supply voltages and low power dissipation. The most important parameters of 1st, 2nd and 3rd orders, i.e. input impedance (Rin), -3 dB bandwidth (BW), power dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as:
1st order: Rin (52.4 Ω), BW (733.7 MHz), Pd (225.6 µW), Ro (105.6 kΩ)
2nd order: Rin (3.8 Ω), BW (576.4 MHz), Pd (307 µW), Ro (106.4 kΩ)
3rd order: Rin (0.34 Ω), BW (566.9 MHz), Pd (535.6 µW), Ro (118.2 kΩ)
And in Post-layout plus Monte Carlo results as:
1st order: Rin (59.9 Ω), BW (609.6 MHz), Pd (212.4 µW), Ro (106.9 kΩ)
2nd order: Rin (11.3 Ω), BW (529.3 MHz), Pd (389.9 µW), Ro (109.8 kΩ)
3rd order: Rin (5.8 Ω), BW (526.5 MHz), Pd (514.5 µW), Ro (125.5 kΩ)
Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block.

A Current-Mode Single-Resistance-Controlled Oscillator Employing VDCC and All Grounded Passive Elements
T. S. Arora,
Volume 16, Issue 2 (6-2020)
Abstract
Realization of a novel single-resistance-controlled oscillator, employing an active element and all grounded passive elements, is the purpose of this manuscript. With requirements for completing the design being only a single Voltage Differencing Current Conveyor and four grounded passive components, it is also a preferable choice for integrated circuit implementation. The designed circuit has an independent control of the frequency of oscillation and current mode output can be achieved from high impedance port, explicitly. Simulation results are presented using PSPICE software along with the regular mathematical analysis. At last experimental verification of the proposed circuit is shown using commercially available integrated circuits.

Li-Ion Battery Charger Interface Circuit with Fast and Safe Charging for Portable Electronic Devices
A. Rahali, K. El Khadiri, A. Tahiri,
Volume 19, Issue 1 (3-2023)
Abstract
In this paper, a Li-Ion Battery Charger Interface (BCI) circuit with fast and safe charging for portable electronic devices is proposed. During the charging of Li-Ion battery, current spikes due to asynchronous control signals, and temperature are factors that greatly affect battery performances and life. This circuit has the following features: prevents current spikes and also incorporates a permanent battery temperature monitoring block. The BCI uses a dual current source and generates a constant current in a large current mode of 1.5 A, further reducing charging time. The proposed BCI was designed and simulated in Cadence Virtuoso using TSMC 180 nm technology. The simulation results of the control signals show that the proposed architecture was able to eliminate the current drifts and keep the battery temperature within the normal operating range.

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.