Showing 3 results for Digital Signal Processing
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Volume 1, Issue 1 (1-2005)
Abstract
In an environment such as underwater channel where placing test equipments are
difficult to handle, it is much practical to have hardware simulators to examine suitably
designed transceivers (transmitter/receiver). The simulators of this kind will then allow
researchers to observe their intentions and carry out repetitive tests to find suitable digital
coding/decoding algorithms.
In this paper, a simplified shallow water digital data transmission system is first introduced.
The transmission channel considered here is a stochastic DSP hardware model in which
signal degradations leads to a severe distortion in phase and amplitude (fades) across the
bandwidth of the received signal. A computer base-band channel model with frequency
non-selective feature is derived by the authors [10-11]. This system was based on fullraised
cosine channel modelling and proved to be the most suitable for vertical and shortrange
underwater communication csdfher), with a reflected path (specula component, when
the acoustic hydrophone receives reflected signals from surface and bottom of the sea) and
a random path (diffused component, when the acoustic hydrophone receives scattered
signals from the volume of the sea). The model assumed perfect transmitter-receiver
synchronization but utilized realistic channel time delays, and demonstrated the timevarying
characteristics of an underwater acoustic channel observed in practice. In this
paper, they are used to provide a full system simulation in order to design an adaptive
receiver employing the most advanced digital signal processing techniques in hardware to
predict realizable error performances.
A. Pathan, T. Memon,
Volume 17, Issue 4 (12-2021)
Abstract
FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. The multiplier is a core element of the DSP systems, and in implementing a memory-based multiplier, it is observed that one of the operands is kept constant, hence leading the design to a constant-coefficient multiplication. This paper shows Virtex-7 FPGA’s dual-port ROM-based implementation of an 8x8 variable-coefficient multiplier that may be used in several simple to complex DSP applications. The novelty of the proposed design is to configure the block ROM in dual-port mode and, hence, get four partial products in two clock cycles and introduce two unconventional adder approaches for partial product addition. This approach leads to fully resource utilization and the provision of a variable-coefficient multiplier. The work also shows the comparison of proposed architecture with already existing memory-based implementations and concludes the work as a novel step towards the efficient memory-based implementation of multiplier core.
Aws Alazawi, Huda Jameel, Mohammed Mohsen,
Volume 20, Issue 2 (6-2024)
Abstract
This study explores the use of distortion product otoacoustic emission (DPOAE) as a hearing screening modality for newborns and adults with hearing impairment. The goal is to improve cochlear response by developing digital filter characteristics to make it consistent for specialists to make accurate diagnoses. To accomplish this, the proposed system consists of a DPOAE ER-10C as stimulation and cochlear response probe, a digital signal processor, an oscilloscope, PC, and audio cables. Real-time distortion product frequency components were extracted using a signal processor of TMS320C6713. To validate the system, a senior medical physicist at Baghdad Medical City in Iraq conducted a study with five hearing-normal volunteers ages 38 and 55 at the center for hearing and communication. The results showed an ability to extract distortion product components in real-time implementation, with the superiority of shape parameters greater than 0.5. In addition, the quantization of filter coefficients was compared for both floating-point arithmetic and fixed-point arithmetic. Noisy environment-based noise reduction techniques have to be investigated by considering the implementation of robust digital signal processing techniques. Finally, the proposed system would contribute to advancements in hearing screening and treatment for those with hearing impairment.
