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Showing 4 results for Field Effect Transistor
Application of Neural Space Mapping for Modeling Ballistic Carbon Nanotube Transistors
R. Yousefi, M. K. Moravvej-Farshi, K. Saghafi,
Volume 6, Issue 2 (6-2010)
Abstract
In this paper, using the neural space mapping (NSM) concept, we present a SPICE-compatible modeling technique to modify the conventional MOSFET equations, to be suitable for ballistic carbon nanotube transistors (CNTTs). We used the NSM concept in order to correct conventional MOSFET equations so that they could be used for carbon nanotube transistors. To demonstrate the accuracy of our model, we have compared our results with those obtained by using open-source software known as FETToy. This comparison shows that the RMS errors in our calculated IDS, under various conditions, are smaller than the RMS errors in IDS values calculated by the existing analytical models published by others.
Ultra-Low Power 5T-SRAM Cell Design using different CNTFET for exploiting Read/Write Assist Techniques
G. S. Kumar, G. Mamatha,
Volume 19, Issue 1 (3-2023)
Abstract
In today's technological environment, designing the Static Random Access Memory (SRAM) is most vital and critical memory devices. In this manuscript, two kinds of 5TSRAM are designed using different CNTFET such as Dual-ChiralityGate all around (GAA) CNTFET and Ballistic wrap gate CNTFET based 5T SRAM cell designs for enhancing the read/write assist process. Here, the proposed Dual-ChiralityGAA-CNTFET based 5T-SRAM has two cross-coupled inverters using one access transistor that is connected to the bit line (BL) and word line (WL) through minimum supply voltage. Instead of cross-coupled inverter circuit, the BWG-CNTFET based 5T-SRAM cell is intended for achieving less power and improved read/write assist process. Also, one transistor is executed as low-threshold (LVT) device in the proposed BWG-CNTFET based 5T-SRAM. Thus, proposed two kinds of 5T SRAM cells increases the read/write assist operation and reduce the leakage current/ power. The simulation of the proposed two kinds of 5T SRAM cell is done by HSPICE simulation tool and the performance metrics are calculated. Therefore, the proposed Dual-ChiralityGAA-CNTFET based 5T-SRAM cell design has attained 11.31%, 51.47% lower read delay, 44.44%, 26.33% lower write delay, 36.12%, 45.28% lower read power, 34.5% , 22.41% lower write power, 37.4%, 15.3% higher read SNM and 35.8%, 12.09% higher write SNM than Double gate carbon nanotube field effect transistors (DG CNTFET) and state-of-art method respectively. Similarly, the proposed BWG-CNTFET 5T SRAM cell design has attained 45.53%, 38.77% lower write delay, 56.67%, 45.64% lower read delay, 58.4%, 56.75% lower read power, 49.66%, 28.56% lower write power, 35.32%, 12.7% higher read SNM and 45.8%, 15.6% higher write SNM than Reduced Power with Enhanced Speed (RPES) approach and state-of-art method respectively.

Integration of Quadrature Oscillator and Floating Inductor in FinFET Transistor Design: Innovations and Applications
Arsen Ahmed, Hüseyin Demirel,
Volume 19, Issue 4 (12-2023)
Abstract
In the past twenty years, low-voltage and power design have gained attention in analog VLSI design, particularly for high-performance and portable integrated circuits (ICs). Because of the increasing density of large-scale integration, a single silicon A.S.I. chip could have thousands or even millions of transistors on it. A rise in integration levels led to the development of Fin-type Field Effect Transistor (FinFETs) technology. In this research, an improved circuit design for a floating active inductor (FAI) and quadrature sinusoidal oscillator (QSO) is implemented employing only two active filters, the Z-copy-Voltage Differential Transimpedance Amplifier (Zc-VDTA). The purpose of the FAI is to contain two Zc-VDTA and one resistor with a ground capacitor, and it is easy to integrate the parameters of the Zc-VDTA bias current (IB) through the adjustment of the circuit. In order to verify the dependability of the circuits designed using floating active inductance circuits, a Butterworth fourth-order low-pass filter was created via component replacement. All the simulations have been carried out on 7 nm using linear technology SPICE, and cadence virtuoso tool.
Design and Performance Optimization of a Bi-Channel Ge-GaAs Vertical Tunnel Field Effect Transistor with High Switching Speed and Improved Tunneling Rate
Zahra Ahangari,
Volume 20, Issue 2 (6-2024)
Abstract
In this paper, an innovative vertical bi-channel tunnel field effect transistor is presented that exploits line tunneling mechanism to achieve improved electrical performance. In this device, the source contains germanium, while the channel and drain regions consist of GaAs., which results in a type-II heterostructure with low resistance tunneling barrier. The source region is situated in a vertical position, enclosed by two sidewall channels that encompass a broad area of tunneling. Our proposed design effectively blocks the electric field that is originated from the drain at the tunneling junction, thereby conferring high immunity to drain induced barrier thinning effect. The device that has been suggested offers a significantly greater on-state current, a factor of 144, when compared to the traditional TFET and provides a subthreshold swing of 3mV/dec and an on/off current ratio of 9.76×1010. According to statistical analysis, the design parameters of metal gate workfunction value and source doping concentration are crucial and have the potential to impact device performance. Therefore, selecting the appropriate combination of these parameters is essential. The proposed device serves as a foundation for the development of computing systems that are low in power and high in speed.
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.