Iranian Journal of Electrical and Electronic Engineering

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This paper proposes a novel approach for generation scheduling using sensitivity

characteristic of a Security Analyzer Neural Network (SANN) for improving static security

of power system. In this paper, the potential overloading at the post contingency steadystate

associated with each line outage is proposed as a security index which is used for

evaluation and enhancement of system static security. A multilayer feed forward neural

network is trained as SANN for both evaluation and enhancement of system security. The

input of SANN is load/generation pattern. By using sensitivity characteristic of SANN,

sensitivity of security indices with respect to generation pattern is used as a guide line for

generation rescheduling aimed to enhance security. Economic characteristic of generation

pattern is also considered in the process of rescheduling to find an optimum generation

pattern satisfying both security and economic aspects of power system. One interesting

feature of the proposed approach is its ability for flexible handling of system security into

generation rescheduling and compromising with the economic feature with any degree of

coordination. By using SANN, several generation patterns with different level of security

and cost could be evaluated which constitute the Pareto solution of the multi-objective

problem. A compromised generation pattern could be found from Pareto solution with any

degree of coordination between security and cost. The effectiveness of the proposed

approach is studied on the IEEE 30 bus system with promising results.

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Abstract: Voltage instability is a major threat for security of power systems. Preserving voltage security margin at a certain limit is a vital requirement for today’s power systems. Assessment of voltage security margin is a challenging task demanding sophisticated indices. In this paper, for the purpose of on line voltage security assessment a new index based on the correlation characteristic of network voltage profile is proposed. Voltage profile comprising all bus voltages contains the effect of network structure, load-generation patterns and reactive power compensation on the system behaviour and voltage security margin. Therefore, the proposed index is capable to clearly reveal the effect of system characteristics and events on the voltage security margin. The most attractive feature for this index is its fast and easy calculation from synchronously measured voltage profile without any need to system modelling and simulation and without any dependency on network size. At any instant of system operation by merely measuring network voltage profile and no further simulation calculation this index could be evaluated with respect to a specific reference profile. The results show that the behaviour of this index with respect to the change in system security is independent of the selected reference profile. The simplicity and easy calculation make this index very suitable for on line application. The proposed approach has been demonstrated on IEEE 39 bus test system with promising results showing its effectiveness and applicability.

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Deregulation of power system in recent years has changed static security assessment to the major concerns for which fast and accurate evaluation methodology is needed. Contingencies related to voltage violations and power line overloading have been responsible for power system collapse. This paper presents an enhanced radial basis function neural network (RBFNN) approach for on-line ranking of the contingencies expected to cause steady state bus voltage and power flow violations. Hidden layer units (neurons) have been selected with the growing and pruning algorithm which has the superiority of being able to choose optimal unit’s center and width (radius). A feature preference technique-based class separability index and correlation coefficient has been employed to identify the relevant inputs for the neural network. The advantages of this method are simplicity of algorithm and high accuracy in classification. The effectiveness of the proposed approach has been demonstrated on IEEE 14-bus power system.

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Differential Power Analysis (DPA) implies measuring the supply current of a cipher-circuit in an attempt to uncover part of a cipher key. Cryptographic security gets compromised if the current waveforms obtained correlate with those from a hypothetical power model of the circuit. As FPGAs are becoming integral parts of embedded systems and increasingly popular for cryptographic applications and rapid prototyping, it is imperative to consider security on FPGAs as a whole. During last years, there has been a large amount of work done dealing with the algorithmic and architectural aspects of cryptographic schemes implemented on FPGAs, however, there are only a few articles that assess their vulnerability to such attacks which, in practice, pose far a greater danger than algorithmic attacks. This paper first demonstrates the vulnerability of the Advanced Encryption Standard Algorithm (AES) implemented on a FPGA and then presents a novel approach for implementation of the AES algorithm which provides a significantly improved strength against differential power analysis with a minimal additional hardware overhead. The efficiency of the proposed technique was verified by practical results obtained from real implementation on a Xilinx Spartan-II FPGA.

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In this paper we introduce two innovative image and video watermarking algorithms. The paper’s main emphasis is on the use of chaotic maps to boost the algorithms’ security and resistance against attacks. By encrypting the watermark information in a one dimensional chaotic map, we make the extraction of watermark for potential attackers very hard. In another approach, we select embedding positions by a two dimensional chaotic map which enables us to satisfactorily distribute watermark information throughout the host signal. This prevents concentration of watermark data in a corner of the host signal which effectively saves it from being a target for attacks that include cropping of the signal. The simulation results demonstrate that the proposed schemes are quite resistant to many kinds of attacks which commonly threaten watermarking algorithms.

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Unintentional attacks on watermarking schemes lead to degrade the watermarking channel, while intentional attacks try to access the watermarking channel. Therefore, watermarking schemes should be robust and secure against unintentional and intentional attacks respectively. Usual security attack on watermarking schemes is the Known Message Attack (KMA). Most popular watermarking scheme with structured codebook is the Scalar Costa Scheme (SCS). The main goal of this paper is to increase security and robustness of SCS in the KMA scenario. To do this, SCS model is extended to more general case. In this case, the usual assumption of an infinite Document to Watermark Ratio (DWR) is not applied. Moreover watermark is assumed to be an arbitrary function of the quantization noise without transgressing orthogonality as in the Costa’s construction. Also, this case is restricted to the structured codebooks. The fundamental trade-off is proved between security and robustness of Generalized SCS (GSCS) in the KMA scenario. Based on this trade-off and practical security attack on SCS, a new extension of SCS is proposed which is called Surjective-SCS (SSCS). In the absence of robustness attack, the SSCS has more security than SCS in the same DWR. However, the SSCS achieves more security and robustness than SCS only in low Watermark to Noise Ratio (WNR) regime or low rate communications.

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