Volume 18, Issue 2 (June 2022)                   IJEEE 2022, 18(2): 66-78 | Back to browse issues page

XML Print

Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
Abolmaali S. Static Timing Analysis for Critical Path Identification in Ternary Logic Circuits. IJEEE 2022; 18 (2) :66-78
URL: http://ijeee.iust.ac.ir/article-1-2245-en.html
Static Timing Analysis for Critical Path Identification in Ternary Logic Circuits
S. Abolmaali
Abstract:   (2289 Views)
In this article, a critical path identification method is proposed for ternary logic circuits. The considered structure for the ternary circuits is based on 2:1 multiplexers. Sensitization conditions for the employed ternary multiplexers are introduced. Moreover, static timing analysis and dynamic programming are utilized in the identification of true and false paths of the circuit for obtaining more realistic results in a reasonable time. An event-driven simulation engine is also developed for confirming the sensitization state of the identified paths. Some ternary arithmetic logic circuits are designed to depict the effectiveness of the proposed identification method. Simulation results show the correctness and efficiency of the proposed method.
Keywords: Critical Path , False Path , Multiplexer , Static Timing Analysis , Ternary Logic
Full-Text [PDF 766 kb]   (1086 Downloads)    
  • Dynamic sensitization conditions for 2:1 ternary multiplexers presented (that are used in constructing the ternary circuits) are introduced.
  • A dynamic programming procedure for identifying the true and false paths of the circuit by using static timing analysis is proposed.
  • An event-driven simulation engine is introduced that is utilized in confirming the sensitization state of the identified paths.
  • Carry skip adders, which are known to have many false paths, in addition to some other arithmetic circuits are designed by ternary logic as benchmark circuits to depict the effectiveness of the proposed identification algorithm in finding the true and false paths of the circuit.

Type of Study: Research Paper | Subject: VLSI
Received: 2021/07/27 | Revised: 2024/05/13 | Accepted: 2022/01/25
Rights and permissions
Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
Creative Commons License
© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.